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Rev 0; 3/08
Secure Microprocessor Chip
General Description
The DS5003 secure microprocessor incorporates sophisticated security features including an array of mechanisms that are designed to resist all levels of threat, including observation, analysis, and physical attack. As a result, a massive effort is required to obtain any information about its memory contents. Furthermore, the "soft" nature of the DS5003 allows frequent modification of the secure information, thereby minimizing the value of any secure information obtained by such a massive effort. The device is an enhanced version of the DS5002FP secure microprocessor chip with additional scratchpad RAM.
Features
8051-Compatible Microprocessor for Secure/Sensitive Applications Access 32kB, 64kB, or 128kB of Nonvolatile SRAM for Program and/or Data Storage 128 Bytes of RAM 128 Bytes of Indirect Scratchpad RAM In-System Programming Through On-Chip Serial Port Can Modify Its Own Program or Data Memory in the End System Firmware Security Features Memory Stored in Encrypted Form Encryption Using On-Chip 64-Bit Key Automatic True Random-Key Generator Self-Destruct Input (SDI) Top Coating Prevents Microprobing Protects Memory Contents from Piracy Crash-Proof Operation Maintains All Nonvolatile Resources for Over 10 Years (at Room Temperature) in the Absence of Power Power-Fail Reset Early Warning Power-Fail Interrupt Watchdog Timer
DS5003
Differences from the DS5002FP
The DS5003 implements only one additional feature from the DS5002FP: it adds 128 bytes of internal scratchpad memory (for a total of 256 bytes) similar to that used in 8032/8052 architectures. This additional memory is accessible through indirect addressing 8051 instructions such as "mov a, @r1," where r1 now can have a value between 0 and 255. It is also usable as stack space for pushes, pops, calls, and returns. Register indirect addressing is used to access the scratchpad RAM locations above 7Fh. It can also be used to reach the lower RAM (0h-7Fh) if needed. The address is supplied by the contents of the working register specified in the instruction. Thus, one instruction can be used to reach many values by altering the contents of the designated working register. Note that only R0 and R1 can be used as pointers. An example of register indirect addressing is as follows:
ANL A, @R0 ;Logical AND the Accumulator with the contents of ;the register pointed to by the value stored in R0
Ordering Information
PART TEMP RANGE 0C to +70C INTERNAL MICRO PROBE SHIELD Yes PINPACKAGE 80 MQFP
DS5003FPM-16+
Applications
PIN Pads Gaming Machines Any Application Requiring Software Protection
+Denotes a lead-free/RoHS-compliant package.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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Secure Microprocessor Chip DS5003
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground..................................-0.3V to (VCC + 0.5V) Voltage Range on VCC Relative to Ground ..........................................................-0.3V to +6.0V Operating Temperature Range.............................40C to +85C Storage Temperature* .......................................-55C to +125C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification.
*Storage temperature is defined as the temperature of the device when VCC = 0V and VLI = 0V. In this state, the contents of SRAM are not battery backed and are undefined.
Note: The DS5003 adheres to all AC and DC electrical specifications published for the DS5002FP.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
(VCC = 5V 10%, TA = 0C to +70C.)
PARAMETER Operating Voltage Minimum Operating Voltage Power-Fail Warning Voltage Lithium Supply Voltage Operating Current at 16MHz Idle-Mode Current at 12MHz Stop-Mode Current Pin Capacitance Output Supply Voltage (VCCO) Output Supply Battery-Backed Mode (VCCO, CE1-CE4, PE1, PE2) Output Supply Current (Note 7) Lithium-Backed Quiescent Current (Note 8) Reset Trip Point in Stop Mode Input Low Voltage Input High Voltage Input High Voltage (RST, XTAL1, PROG) Output Low Voltage at I OL = 1.6mA (Ports 1, 2, 3, PF) VIL VIH1 VIH2 VOL1 SYMBOL VCC VCCMIN VPFW VLI ICC I IDLE I STOP CIN VCCO1 (Note 1) 0C to +70C (Note 1) 0C to +70C (Note 1) (Note 1) (Note 2) 0C to +70C (Note 3) (Note 4) (Note 5) (Notes 1, 2) VCC 0.45 VLI 0.65 75 5 4.00 4.40 -0.3 2.0 3.5 0.15 75 4.25 4.65 +0.8 VCC + 0.3 VCC + 0.3 0.45 CONDITIONS MIN VCCMIN 4.00 4.25 2.5 4.12 4.37 TYP MAX 5.5 4.25 4.50 4.0 36 7.0 80 10 UNITS V V V V mA mA A pF V
VCCO2 ICCO1 ILI
0C to +70C (Notes 1, 6) VCCO = VCC - 0.45V 0C to +70C BAT = 3.0V (0C to +70C) (Note 1) BAT = 3.3V (0C to +70C) (Note 1) (Note 1) (Note 1) (Note 1) (Notes 1, 9)
V mA nA V V V V V
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Secure Microprocessor Chip
DC CHARACTERISTICS (continued)
(VCC = 5V 10%, TA = 0C to +70C.)
PARAMETER Output Low Voltage at I OL = 3.2mA (P0.0-P0.7, ALE, BA0-BA14, BD0-BD7, R/W, CE1N, CE1-CE4, PE1-PE4, VRST) Output High Voltage at I OH = -80A (Ports 1, 2, 3) Output High Voltage at I OH = -400A (P0.0-P0.7, ALE, BA0-BA14, BD0-BD7, R/W, CE1N, CE1-CE4, PE1-PE4, VRST) Input Low Current, VIN = 0.45V (Ports 1, 2, 3) Transition Current 1 to 0, VIN = 2.0V (Ports 1, 2, 3) SDI Input Low Voltage SDI Input High Voltage SDI Pulldown Resistor Input Leakage (P0.0-P0.7, MSEL) RST Pulldown Resistor VRST Pullup Resistor PROG Pullup Resistor SYMBOL CONDITIONS MIN TYP MAX UNITS
DS5003
VOL2
(Note 1)
0.15
0.45
V
VOH1
(Note 1)
2.4
4.8
V
VOH2
(Note 1)
2.4
4.8
V
I IL ITL VILS VIHS RSDI I IL RRE RVR RPR 0.45 < VIN < VCC 0C to +70C 40 4.7 40 (Note 1) (Notes 1, 10) 2.0 25
-50 -500 0.4 VCCO 60 +10 150
A A V V k A k k k
AC CHARACTERISTICS--SDI PIN
(VCC = 0V to 5V, TA = 0C to +70C.)
PARAMETER SDI Pulse Reject (Note 11) SDI Pulse Accept (Note 11) SYMBOL t SPR t SPA CONDITIONS 4.5V < VCC < 5.5V VCC = 0V, VBAT = 2.9V 4.5V < VCC < 5.5V VCC = 0V, VBAT = 2.9V 10 50 MIN TYP MAX 1.3 4 UNITS s s
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Secure Microprocessor Chip DS5003
AC CHARACTERISTICS--EXPANDED BUS-MODE TIMING SPECIFICATIONS
(VCC = 5V 10%, TA = 0C to +70C.) (Figures 1, 2)
PARAMETER Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After RD High Data Float After RD High ALE Low to Valid Data In Valid Address to Valid Data In ALE Low to RD or WR Low Address Valid to RD or WR Low Data Valid to WR Going Low Data Valid to WR High Data Valid After WR High RD Low to Address Float RD or WR High to ALE High SYMBOL 1/tCLK tALPW tAVALL tAVAAV tRDPW tWRPW tRDLDV tRDHDV tRDHDZ tALLVD tAVDV tALLRDL tAVRDL tDVWRL tDVWRH tWRHDV tRDLAZ tRDHALH tCLK - 40 12MHz 16MHz 12MHz 16MHz 12MHz 16MHz 3tCLK - 50 4tCLK - 130 tCLK - 60 7tCLK - 150 7tCLK - 90 tCLK - 50 0 tCLK + 50 12MHz 16MHz 0 2tCLK - 70 8tCLK - 150 8tCLK - 90 9tCLK - 165 9tCLK - 105 3tCLK + 50 CONDITIONS MIN 1.0 2tCLK - 40 tCLK - 40 tCLK - 35 6tCLK - 100 6tCLK - 100 5tCLK - 165 5tCLK - 105 MAX 16.0 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AC CHARACTERISTICS--EXTERNAL CLOCK DRIVE
(VCC = 5V 10%, TA = 0C to +70C.) (Figure 3)
PARAMETER External Clock High Time External Clock Low Time External Clock Rise Time External Clock Fall Time SYMBOL tCLKHPW tCLKLPW tCLKR tCLKF 12MHz 16MHz 12MHz 16MHz 12MHz 16MHz 12MHz 16MHz CONDITIONS MIN 20 15 20 15 20 15 20 15 MAX UNITS ns ns ns ns
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Secure Microprocessor Chip
AC CHARACTERISTICS--POWER-CYCLE TIME
(VCC = 5V 10%, TA = 0C to +70C.) (Figure 4)
PARAMETER Slew Rate from VCCMIN to VLI Crystal Startup Time Power-On Reset Delay SYMBOL tF tCSU t POR MIN 130 (Note 12) 21,504 tCLK MAX UNITS s
DS5003
AC CHARACTERISTICS--SERIAL PORT TIMING (MODE 0)
(VCC = 5V 10%, TA = 0C to +70C.) (Figure 5)
PARAMETER Serial Port Clock Cycle Time Output Data Setup to Rising Clock Edge Output Data Hold After Rising Clock Edge Clock Rising Edge to Input Data Valid Input Data Hold After Rising Clock Edge SYMBOL t SPCLK tDOCH tCHDO tCHDV tCHDIV 0 MIN 12tCLK 10tCLK - 133 2tCLK - 117 10tCLK - 133 MAX UNITS s ns ns ns ns
AC CHARACTERISTICS--BYTE-WIDE ADDRESS/DATA BUS TIMING
(VCC = 5V 10%, TA = 0C to +70C.) (Figure 6)
PARAMETER Delay to Byte-Wide Address Valid from CE1, CE2, or CE1N Low During Op Code Fetch Pulse Width of CE1-CE4, PE1-PE4, or CE1N Byte-Wide Address Hold After CE1, CE2, or CE1N High During Op Code Fetch Byte-Wide Data Setup to CE1, CE2, or CE1N High During Op Code Fetch Byte-Wide Data Hold After CE1, CE2, or CE1N High During Op Code Fetch Byte-Wide Address Hold After CE1-CE4, PE1-PE4, or CE1N High During MOVX Delay from Byte-Wide Address Valid CE1-CE4, PE1-PE4, or CE1N Low During MOVX Byte-Wide Data Setup to CE1-CE4, PE1-PE4, or CE1N High During MOVX (Read) Byte-Wide Data Hold After CE1-CE4, PE1-PE4, or CE1N High During MOVX (Read) Byte-Wide Address Valid to R/W Active During MOVX (Write) SYMBOL tCE1LPA tCEPW tCE1HPA t OVCE1H tCE1HOV tCEHDA tCELDA tDACEH tCEHDV tAVRWL 4tCLK - 35 2tCLK - 20 1tCLK + 40 0 4tCLK - 30 4tCLK - 35 1tCLK + 40 0 3tCLK - 35 MIN MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns
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Secure Microprocessor Chip DS5003
AC CHARACTERISTICS--BYTE-WIDE ADDRESS/DATA BUS TIMING (continued)
(VCC = 5V 10%, TA = 0C to +70C.) (Figure 6)
PARAMETER Delay from R/W Low to Valid Data Out During MOVX (Write) Valid Data Out Hold Time from CE1-CE4, PE1-PE4, or CE1N High Valid Data Out Hold Time from R/W High Write Pulse Width (R/W Low Time) SYMBOL tRWLDV tCEHDV tRWHDV tRWLPW MIN 20 1tCLK - 15 0 6tCLK - 20 MAX UNITS ns ns ns ns
RPC AC CHARACTERISTICS--DBB READ
(VCC = 5V 10%, TA = 0C to +70C.) (Figure 7)
PARAMETER CS, A0 Setup to RD CS, A0 Hold After RD RD Pulse Width CS, A0 to Data Out Delay RD to Data Out Delay RD to Data Float Delay SYMBOL tAR tRA tRR tAD tRD tRDZ 0 MIN 0 0 160 130 130 85 MAX UNITS ns ns ns ns ns ns
RPC AC CHARACTERISTICS--DBB WRITE
(VCC = 5V 10%, TA = 0C to +70C.) (Figure 7)
PARAMETER CS, A0 Setup to WR CS Hold After WR A0 Hold After WR WR Pulse Width Data Setup to WR Data Hold After WR SYMBOL tAW tWA tWA tWW tDW tWD MIN 0 0 20 160 130 20 MAX UNITS ns ns ns ns ns ns
AC CHARACTERISTICS--DMA
(VCC = 5V 10%, TA = 0C to +70C.)
PARAMETER DACK to WR or RD RD or WR to DACK DACK to Data Valid RD or WR to DRQ Cleared SYMBOL tACC tCAC tACD tCRQ MIN 0 0 0 130 110 MAX UNITS ns ns ns ns
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Secure Microprocessor Chip DS5003
AC CHARACTERISTICS--PROG
(VCC = 5V 10%, TA = 0C to +70C.)
PARAMETER PROG Low to Active PROG High to Inactive SYMBOL t PRA t PRI MIN 48 48 MAX UNITS Clocks Clocks
All voltages are referenced to ground. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10ns, VIL = 0.5V; XTAL2 disconnected; RST = Port 0 = VCC, MSEL = VSS. Note 3: Idle mode, IIDLE, is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10ns, VIL = 0.5V; XTAL2 disconnected; Port 0 = VCC, RST = MSEL = VSS. Note 4: Stop mode, ISTOP, is measured with all output pins disconnected; Port 0 = VCC; XTAL2 not connected; RST = MSEL = XTAL1 = VSS. Note 5: Pin capacitance is measured with a test frequency: 1MHz, TA = +25C. This specification is characterized but not production tested. Note 6: VCCO2 is measured with VCC < VLI and a maximum load of 10A on VCCO. Note 7: ICCO1 is the maximum average operating current that can be drawn from VCCO in normal operation. Note 8: ILI is the current drawn from the VLI input when VCC = 0V and VCCO is disconnected. Battery-backed mode is 2.5V VBAT 4.0; VCC VBAT; VSDI should be VILS for IBAT max. Note 9: PF pin operation is specified with VBAT 3.0V. Note 10: VIHS minimum is 2.0V or VCCO, whichever is lower. Note 11: SDI is deglitched to prevent accidental destruction. The pulse must be longer than tSPR to pass the deglitcher, but SDI is not guaranteed unless it is longer than tSPA. Note 12: Crystal startup time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user should check with the crystal vendor for a worst-case specification on this time. Note 1: Note 2:
tALPW ALE
tRDHALH
tALLVD tALLRDL RD tAVALL tRDLDV tRDHDZ tAVAAV tRDLAZ tRDHDV DATA IN A7-A0 (PCL) INSTR IN tRDPW
PORT 0
A7-A0 (Rn OR DPL) tAVRDL tAVDV
PORT 2
P2.7-P2.0 OR A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 1. Expanded Data Memory Read Cycle
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Secure Microprocessor Chip DS5003
tRDHALH
ALE
tALLRDL
tWRPW
WR tDVWRL tAVAAV tAVALL A7-A0 (Rn OR DPL) tDVWRH A7-A0 (PCL) INSTR IN tWRHDV
PORT 0
DATA OUT
tAVRDL
PORT 2
P2.7-P2.0 OR A15-A8 FROM PDH
A15-A8 FROM PCH
Figure 2. Expanded Data Memory Write Cycle
tCLKHPW tCLKF
tCLKLPW tCLKR 1/tCLK
Figure 3. External Clock Timing
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Secure Microprocessor Chip DS5003
VCC VPFW VCCMIN
VLI
tF INTERRUPT SERVICE ROUTINE
tCSV
CLOCK OSC
tPOR
INTERNAL RESET
LITHIUM CURRENT
Figure 4. Power-Cycle Timing
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Secure Microprocessor Chip DS5003
0 1 2 3 4 5 6 7 8
ALE
tSPCLK CLOCK tDOCH tCHDO DATA OUT 0 1 2 3 4 5 6 7 SET TI
WRITE TO SBUF REGISTER tCHDIV INPUT DATA VALID CLEAR RI VALID
tCHDV
SET RI VALID VALID VALID VALID VALID
Figure 5. Serial Port Timing (Mode 0)
MACHINE CYCLE 1 XTAL2 2 3 4 5 6 1 2
MACHINE CYCLE 3 4 5 6 6 1 2
MACHINE CYCLE 3 4 5 6
ALE R/W tRWLPW tAVRWL PC OUT tCEL1LPA tCEL1HPA CE1, CE2, OR CE1N CE1, CE2, CE3, CE4, PE1, PE2, PE3, PE4, OR CE1N BD0-BD7 DATA IN tCEPW tOVCE1H tCE1HOV DATA IN DATA IN tDACEH tCEHDV DATA tRWLDV DATA OUT tCEPW tRWHDV tCEHDV PC OUT DPL AND (DPH OR P2 SFR OUT) tCELDA tCEHDA PC OUT DPL AND (DPH OR P2 SFR OUT) tCELDA tCEHDA PC OUT
BA0-BA14
Figure 6. Byte-Wide Bus Timing
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Secure Microprocessor Chip DS5003
READ OPERATION CS OR A0 tAR tRR RD tRD DATA VALID tRDZ tRA
tAD DATA
WRITE OPERATION CS OR A0 tAW WR tDW DATA DATA VALID tWD tWW tWA
DMA DACK
RD tACC WR tACC tCAC tCAC
DATA tACD DRQ tCRQ
VALID
VALID
tCRQ
Figure 7. RPC Timing Mode
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Secure Microprocessor Chip DS5003
Pin Description
PIN 13 NAME POWER PINS VCC Power Supply, +5V VCC Output. This is switched between VCC and VLI by internal circuits based on the level of VCC. When power is above the lithium input, power is drawn from VCC. The lithium cell remains isolated from a load. When VCC is below VLI, VCCO switches to the VLI source. VCCO should be connected to the VCC pin of an SRAM. Lithium Voltage Input. Connect to a lithium cell greater than VLIMIN and no greater than VLIMAX as shown in the electrical specifications. Nominal value is +3V. Logic Ground GENERAL-PURPOSE I/O PINS 11 9 7 5 1 79 77 75 15 17 19 21 25 27 29 31 49 50 51 56 58 60 64 66 36 38 39 40 41 44 45 46 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD FUNCTION
12
VCCO
54 52
VLI GND
General-Purpose I/O Port 0. This port is open drain and cannot drive a logic 1. It requires external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in this mode, it does not require pullups.
General-Purpose I/O Port 1
General-Purpose I/O Port 2. Also serves as the MSB of the expanded address bus.
General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on-board UART. This pin should not be connected directly to a PC COM port. General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on-board UART. This pin should not be connected directly to a PC COM port. General-Purpose I/O Port General-Purpose I/O Port General-Purpose I/O Port General-Purpose I/O Port General-Purpose I/O Port General-Purpose I/O Port Pin 3.2. Pin 3.3. Pin 3.4. Pin 3.5. Pin 3.6. Pin 3.7. Also Also Also Also Also Also serves serves serves serves serves serves as the active-low external interrupt 0. as the active-low external interrupt 1. as the timer 0 input. as the timer 1 input. as the write strobe for expanded bus operation. as the read strobe for expanded bus operation.
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Secure Microprocessor Chip
Pin Description (continued)
PIN 37 35 33 30 28 26 24 20 6 4 76 80 18 8 16 55 57 59 61 65 67 69 71 70 NAME BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BA11 BA12 BA13 BA14 BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 ALE Address Latch Enable. Used to demultiplex the multiplexed expanded address/data bus on port 0. This pin is normally connected to the clock input on a '373 type transparent latch. Read/Write (Active Low). This signal provides the write enable to the SRAMs on the byte-wide bus. It is controlled by the memory map and partition. The blocks selected as program (ROM) are write protected. Active-Low Chip-Enable 1. This is the primary decoded chip enable for memory access on the byte-wide bus. It connects to the chip-enable input of one SRAM. CE1 is lithium-backed. It remains in a logic-high inactive state when VCC falls below VLI. Nonbattery-Backed Version of CE1. It is not generally useful because the DS5003 cannot be used with EPROM due to its encryption. Active-Low Chip-Enable 2. This chip enable is provided to access a second 32kB block of memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, the microcontroller converts CE2 into A16 for a 128kB x 8 SRAM. CE2 is lithium-backed and remains at a logic-high when VCC falls below VLI. Active-Low Chip-Enable 3. This chip enable is provided to access a third 32kB block of memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, the microcontroller converts CE3 into A15 for a 128kB x 8 SRAM. CE3 is lithium backed and remains at a logic-high when VCC falls below VLI. Byte-Wide Data Bus Bits 7-0. This 8-bit bidirectional bus is combined with the nonmultiplexed address bus (BA14-BA0) to access external SRAM. Decoding is performed on CE1 and CE2. Read/write access is controlled by R/W. D7-D0 connect directly to an SRAM and optionally to a real-time clock or other peripheral. Byte-Wide Address Bus Bits 14-0. This bus is combined with the nonmultiplexed data bus (BD7-BD0) to access external SRAM. Decoding is performed using CE1-CE4. Therefore, BA15 is not actually needed. Read/write access is controlled by R/W. BA14-BA0 connect directly to an 8kB, 32kB, or 128kB SRAM. If an 8kB SRAM is used, BA13 and BA14 are unconnected. If a 128kB SRAM is used, the microcontroller converts CE2 and CE3 to serve as A16 and A15, respectively. FUNCTION BYTE-WIDE BUS INTERFACE PINS
DS5003
10
R/W
74
CE1
72
CE1N
2
CE2
63
CE3
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Secure Microprocessor Chip DS5003
Pin Description (continued)
PIN 62 NAME CE4 FUNCTION Active-Low Chip-Enable 4. This chip enable is provided to access a fourth 32kB block of memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is unused. CE4 is lithium-backed and remains at a logic-high when VCC falls below VLI. Active-Low Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when the PES bit is set to logic 1. Commonly used to chip enable a byte-wide real-time clock such as the DS1283. PE1 is lithium backed and remains at a logic-high when VCC falls below VLI. Connect PE1 to battery-backed circuitry only. Active-Low Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when the PES bit is set to logic 1. PE2 is lithium backed and remains at a logic-high when VCC falls below VLI. Connect PE2 to battery-backed circuitry only. Active-Low Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when the PES bit is set to a logic 1. PE3 is not lithium backed and can be connected to any type of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to maintain the chip enable in an inactive state when VCC < VLI. Active-Low Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when the PES bit is set to logic 1. PE4 is not lithium backed and can be connected to any type of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to maintain the chip enable in an inactive state when VCC < VLI. Memory Select. This signal controls the memory size selection. When MSEL = +5V, the DS5003 expects to use 32kB x 8 SRAMs. When MSEL = 0V, the DS5003 expects to use a 128kB x 8 SRAM. MSEL must be connected regardless of partition, mode, etc. CLOCK PINS 47, 48 XTAL2, XTAL1 Crystal Connections. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output. RESET, STATUS, AND SELF-DESTRUCT PINS 34 RST Active-High Reset Input. A logic 1 applied to this pin activates a reset state. This pin is pulled down internally so this pin can be left unconnected if not used. An RC power-on reset circuit is not needed and is not recommended. Invokes the Bootstrap Loader on Falling Edge. This signal should be debounced so that only one edge is detected. If connected to ground, the microcontroller enters bootstrap loading on power-up. This signal is pulled up internally. Reset State Active Due to Low VCC. This I/O pin (open drain with internal pullup) indicates that the power supply (VCC) has fallen below the VCCMIN level and the microcontroller is in a reset state. When this occurs, the DS5003 drives this pin to logic 0. Because the microcontroller is lithium backed, this signal is guaranteed even when VCC = 0V. Because it is an I/O pin, it also forces a reset if pulled low externally. This allows multiple parts to synchronize their powerdown resets. Lithium Backup Active. This output goes to a logic 0 to indicate that the microcontroller has switched to lithium backup. This corresponds to VCC < VLI. Because the microcontroller is lithium backed, this signal is guaranteed even when VCC = 0V. The normal application of this signal is to control lithium-powered current to isolate battery-backed functions from nonbatterybacked functions. Self-Destruct Input. An active high on this pin causes an unlock procedure. This results in the destruction of vector SRAM, encryption keys, and the loss of power from VCCO. This pin should be grounded if not used. MISCELLANEOUS PINS 68, 73 N.C. No Connection
78
PE1
3
PE2
22
PE3
23
PE4
14
MSEL
32
PROG
42
VRST
43
PF
53
SDI
14
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Secure Microprocessor Chip
Detailed Description
The DS5003 implements a security system that loads and executes application software in encrypted form. Up to 128kB of standard SRAM (64kB program + 64kB data) can be accessed by its byte-wide bus. This SRAM is converted by the DS5003 into lithium-backed nonvolatile storage for program and data. Data can be maintained for up to 10 years at room temperature with a very small lithium cell. As a result, the contents of the SRAM and the execution of the software appear unintelligible to the outside observer. The encryption algorithm uses an internally stored and protected key. Any attempt to discover the key value results in its erasure, rendering the encrypted contents of the SRAM useless. The secure microprocessor chip provides a strong software-encryption algorithm that incorporates elements of DES encryption. The encryption is based on a 64-bit key word, and the key can only be loaded from an onchip true random-number generator. As a result, the user never knows the true key value. A self-destruct input (SDI) pin is provided to interface to external tamper-detection circuitry. With or without the presence of VCC, activation of the SDI pin has the same effect as resetting the security lock: immediate erasure of the key word and the 48-byte vector SRAM area. In addition, an optional top coating of the die prevents access of information using microprobing techniques. When implemented as a part of an overall secure system design, a system based on the DS5003 can typically provide a level of security that requires more time and resources to defeat than necessary for unauthorized individuals who have reason to try. Figure 8 is a block diagram illustrating the internal architecture of the DS5003. The DS5003 operates in an identical fashion to the DS5002FP, except where noted in text. 4) Load application software. 5) Set security lock. 6) Exit loader by taking the PROG pin high again. Loading of application software into the program/data SRAM is performed while the DS5003 is in its bootstrap load mode. Loading is only possible when the security lock is clear. If the security lock was previously set, it must be cleared by issuing the U command from the bootstrap loader. Clearing the security lock instantly clears the previous key word and the contents of the vector SRAM. In addition, the bootstrap ROM writes zeros into the first 32kB of external SRAM. The user's application software is loaded into user-supplied external SRAM by the L command in "scrambled" form through on-chip encryptor circuits. Each external SRAM address is an encrypted representation of an onchip logical address. Thus, the sequential instructions of an ordinary program or data table are stored nonsequentially in SRAM memory. The contents of the program/data SRAM are also encrypted. Each byte in SRAM is encrypted by a key- and address-dependent encryptor circuit such that identical bytes are stored as different values in different memory locations. The encryption of the program/data SRAM is dependent on an on-chip 64-bit key word. The key is automatically generated by the ROM firmware just prior to the time that the application software is loaded, and is retained as nonvolatile information in the absence of VCC by the lithium-backup circuits. After the application software loading is complete, the key is protected by setting the on-chip security lock, which is also retained as nonvolatile information in the absence of VCC. Any attempt to tamper with the key word and, thereby, gain access to the true program/data SRAM contents results in the erasure of the key word as well as the SRAM contents. During execution of the application software, logical addresses on the DS5003 that are generated from the program counter or data pointer registers are encrypted before they are presented on the byte-wide address bus. Op codes and data are read back and decrypted before they are operated on by the CPU. Similarly, data values written to the external NV SRAM storage during program execution are encrypted before they are presented on the byte-wide data bus during the write operation. This encryption/decryption process is performed in real time such that no execution time is lost, so the operation of the encryptor circuitry is transparent to the application software. The DS5003's security features are always enabled.
DS5003
Secure Operation Overview
The DS5003 incorporates encryption of the activity on its byte-wide address/data bus to prevent unauthorized access to the program and data information contained in the external SRAM. Loading an application program in this manner is performed by the bootstrap loader using the general sequence described as follows: 1) Activate bootstrap loader by asserting the PROG pin low for at least 48 clocks. 2) Clear security lock. 3) Set memory map configuration. These settings are identical to those used for DS5002FP-based designs.
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15
Secure Microprocessor Chip DS5003
WATCHDOG TIMER BYTEADDRESS WIDE BUS DATA INTERFACE
XTAL1 XTAL2
OSC
R/W 4 16 BA0-BA14 8 BD0-BD7 4 PE1-PE4 CE1-CE4
ADDRESS/ DATA ENCRYPTORS RST ALE PROG TIMING AND BUS CONTROL
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
SPECIAL FUNCTION REGISTERS PORT 0
ENCRYPTION KEYS
SDI
DATA REGISTERS WITH ENHANCED INDIRECT ADDRESSING (256 BYTES)
POWER MONITOR
VCC VCCO PF VRST VLI
PORT 1
VECTOR RAM (48 BYTES)
CPU
PORT 2
BOOTSTRAP LOADER ROM
DS5003
PORT 3
TXD RXD TIMER 0 TIMER 1 INT0 INT1
Figure 8. Block Diagram
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Secure Microprocessor Chip
Security Circuitry
Figure 9 shows the on-chip functions associated with the DS5003's software security feature. Encryption logic consists of an address encryptor and a data encryptor. Although each encryptor uses its own algorithm for encrypting data, both depend on the 64-bit key word that is contained in the encryption key registers. Both the encryptors operate during loading of the application software and also during its execution. The address encryptor translates each logical address, i.e., the normal sequence of addresses that are generated in the logical flow of program execution, into an encrypted address (or physical address) at which the byte is actually stored. Each time a logical address is generated, either during program loading or during program execution, the address encryptor circuitry uses the value of the 64-bit key word and of the address itself to form the physical address, which are presented on the address lines of the SRAM. The encryption algorithm is such that there is one and only one physical address for every possible logical address. The address encryptor operates over the entire memory range, which is configured during bootstrap loading for access on the byte-wide bus. As bootstrap loading of the application software is performed, the data encryptor logic transforms the op code, operand, or data byte at any given memory location into an encrypted representation. As each byte is read back to the CPU during program execution, the internal data encryptor restores it to its original value. When a byte is written to the external nonvolatile program/data SRAM during program execution, that byte is stored in encrypted form as well. The data encryption logic uses the value of the 64-bit key, the logical address to which the data is being written, and the value of the data itself to form the encrypted data, which is written to the nonvolatile program/data SRAM. The encryption algorithm is repeatable, such that for a given data value, encryption key value, and logical address the encrypted byte is always the same. However, there are many possible encrypted data values for each possible true-data value due to the algorithm's dependency on the values of the logical address and encryption key.
DS5003
PROGRAM COUNTER
DATA POINTER ENCRYPTED BYTE-WIDE ADDRESS BUS
SECURE INTERNAL ADDRESS BUS
ADDRESS ENCRYPTOR 16
BOOTSTRAP LOADER
RANDOMNUMBER GENERATOR SECURITY LOCK 64-BIT ENCRYPTION KEY
EXTERNAL BYTE-WIDE RAM
ENCRYPTED BYTE-WIDE DATA BUS SECURE INTERNAL DATA BUS DATA ENCRYPTOR 8
SDI (SELF-DESTRUCT INPUT)
Figure 9. Security Circuitry
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Secure Microprocessor Chip
When the application software is executed, the DS5003's internal CPU operates as normal. Logical addresses are calculated for op code fetch cycles and also data read and write operations. The DS5003 can perform address encryption on logical addresses as they are generated internally during the normal course of program execution. In a similar fashion, data is manipulated by the CPU in its true representation. However, data is also encrypted when it is written to the external program/data SRAM, and is restored to its original value when it is read back. When an application program is stored in the previously described format, it is virtually impossible to disassemble op codes or to convert data back into its true representation. Address encryption has the effect that the op codes and data are not stored in the contiguous form in which they were assembled, but rather in seemingly random locations in memory. This effect makes it virtually impossible to determine the normal flow of the program. As an added protection measure, the address encryptor also generates dummy read-access cycles whenever time is available during program execution. SRAM. This scheme prevents characterization of the encryption algorithm by continuously loading new, known keys. It also frees the user from the burden of protecting the key selection process. The random-number generator circuit uses the asynchronous frequency differences of two internal ring oscillators and the processor master clock (determined by XTAL1 and XTAL2). As a result, a true random number is produced.
DS5003
Vector RAM
A 48-byte vector RAM area is incorporated on-chip, and is used to contain the reset and interrupt vector code in the DS5003. It is included in the architecture to help ensure the security of the application program. If reset and interrupt vector locations were accessed from the external nonvolatile program/data RAM during the execution of the program, it would be possible to determine the encrypted value of known addresses. This could be done by forcing an interrupt or reset condition and observing the resulting addresses on the byte-wide address/data bus. For example, it is known that when a hardware reset is applied, the logical program address is forced to location 0000h and code is executed starting from this location. It would then be possible to determine the encrypted value (or physical address) of the logical address value 0000h by observing the address presented to the external SRAM following a hardware reset. Interrupt vector address relationships could be determined in a similar fashion. By using the on-chip vector RAM to contain the interrupt and reset vectors, it is impossible to observe such relationships. The vector RAM eliminates the unlikely possibility that an application program could be deciphered by observing vector address relationships. Note that the dummy accesses mentioned are conducted while fetching from vector RAM. The vector RAM is automatically loaded with the user's reset and interrupt vectors from the Intel hex file during bootstrap loading.
Dummy Read Cycles
Like the DS5002FP, the DS5003 generates a dummy read-access cycle to nonsequential addresses in external SRAM memory whenever time is available during program execution. This action further complicates the task of determining the normal flow of program execution. During these pseudorandom dummy cycles, the SRAM is read to all appearances, but the data is not used internally. Through the use of a repeatable exchange of dummy and true read cycles, it is impossible to distinguish a dummy cycle from a real one.
Encryption Algorithm
The DS5003 incorporates a proprietary hardware algorithm that performs the scrambling of address and data on the byte-wide bus to the SRAM. Improvements include the following: * 64-bit encryption key (protected by the security lock function). * Incorporation of DES-like operations to provide a greater degree of nonlinearity. * Customizable encryption.
Security Lock
Once the application program has been loaded into the DS5003's external and vector RAM, the security lock can be enabled by issuing the Z command in the bootstrap loader. While the security lock is set, no further access to program/data information is possible by the on-chip ROM. Access is prevented by both the bootstrap loader firmware and the DS5003 encryptor circuits. Access to the SRAM can only be regained by clearing the security lock by the U command in the bootstrap
Encryption Key
As previously described, the on-chip 64-bit encryption key is the basis of both the address and data encryptor circuits. When the loader is given certain commands, the key is generated from an on-chip hardware random-number generator. This action is performed just prior to actually loading the code into the external
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Secure Microprocessor Chip
loader. This action triggers several events that defeat tampering. First, the encryption key is instantaneously erased. Without the encryption key, the DS5003 can no longer decrypt the contents of the SRAM. Therefore, the application software can no longer be correctly executed, nor can it be read back in its true form by the bootstrap loader. Second, the vector RAM area is also instantaneously erased, so that the reset and vector information is lost. Third, the bootstrap loader firmware sequentially erases the encrypted SRAM area. Lastly, the loader creates and loads a new random key. The security lock bit is constructed using a multiple-bit latch that is interlaced for self-destruction in the event of tampering. The lock is designed to set up a "domino effect" such that erasure of the bit results in an unstoppable sequence of events that clears critical data including encryption key and vector RAM. In addition, this bit is protected from probing by the top-coating feature. 256-byte scratchpad RAM area are automatically overwritten with zeros and then used for variable storage for the bootstrap firmware. Also, a set of 8 bytes is generated using the random-number generator circuitry and saved as a potential word for the 64-bit encryption key. Any read or write operation to the DS5003's external program/data SRAM can only take place if the security lock bit is in a cleared state. Therefore, the first step in loading a program should be the clearing of the security lock bit through the U command.
DS5003
Table 1. Serial Bootstrap Loader Commands
COMMAND C D F G L N P R T U V W Z FUNCTION Return CRC-16 of the program/data SRAM. Dump RAM memory specified by MSL bit as Intel hex format. Fill program/data SRAM. Get data from P0, P1, P2, and P3. Load Intel hex file. Set freshness seal--all program and data is lost. Put data into P0, P1, P2, and P3. Read status of SFRs (MCON, RPCTL, MSL). Trace (echo) incoming Intel hex code. Clear security lock. Verify program/data memory with incoming Intel hex data. Write special function registers (MCON, RPCTL, MSL). Set security lock.
Self-Destruct Input (SDI)
The self-destruct input (SDI) pin is an active-high input that is used to reset the security lock in response to a variety of user-defined external events. The SDI input is intended to be used with external tamper-detection circuitry. It can be activated with or without operating power applied to the VCC pin. Activation of the SDI pin instantly resets the security lock and causes the same sequence of events previously described for this action. In addition, power is momentarily removed from the byte-wide bus interface including the V CC pin, resulting in the loss of data in external SRAM.
Top-Layer Coating
The DS5003M is provided with a special top-layer coating that is designed to prevent a probe attack. This coating is implemented with second-layer metal added through special processing of the microcontroller die. This additional layer is not a simple sheet of metal, but rather a complex layout that is interwoven with power and ground, which are in turn connected to logic for the encryption key and the security lock. As a result, any attempt to remove the layer or probe through it results in the erasure of the security lock and/or the loss of encryption key bits.
Execution of certain bootstrap loader commands result in the loading of the newly generated 64-bit random number into the encryption key word. These commands are as follows: Fill F Load L Dump D Verify V CRC C Execution of the Fill and Load commands load the encrypted data into SRAM using encryption keys from the newly generated key word. The subsequent execution of the Dump command within the same bootstrap session causes the contents of the encrypted SRAM to
19
Bootstrap Loading
Initial loading of application software into the DS5003 is performed by firmware within the on-chip bootstrap loader communicating with a PC by the on-chip serial port. Table 1 summarizes the commands accepted by the bootstrap loader. When the bootstrap loader is invoked, portions of the
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Secure Microprocessor Chip
be read out and transmitted back to the host PC in decrypted form. Similarly, execution of the Verify command within the same bootstrap session causes the incoming absolute hex data to be compared against the true contents of the encrypted SRAM, and the CRC command returns the CRC value calculated from the true contents of the encrypted SRAM. As long as any of these commands are executed within the same bootstrap session, the loaded key value remains the same and the contents of the encrypted program/data SRAM can be read or written normally and freely until the security lock bit is set. When the security lock bit is set using the Z command, no further access to the true SRAM contents is possible using any bootstrap command or by any other means. A more extensive explanation of the serial loader operation can be found in the Secure Microcontroller User's Guide (www.maxim-ic.com/SecureUG).
DS5003
Instruction Set
The DS5003 executes an instruction set that is objectcode compatible with the industry-standard 8051 microcontroller. As a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the DS5003. A complete description of the instruction set and operation is provided in the Secure Microcontroller User's Guide.
Memory Organization
Figure 10 illustrates the memory map accessed by the DS5003. The entire 64kB of program and 64kB of data are potentially available to the byte-wide bus. This preserves the I/O ports for application use. The user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program range and data range. Any area not mapped into the SRAM is
PROGRAM MEMORY FFFFh
DATA MEMORY (MOVX) 64kB
PROGRAM RANGE DATA RANGE
NV RAM PROGRAM
NV RAM DATA
0000h
LEGEND: = BYTE-WIDE BUS ACCESS (ENCRYPTED) = EXPANDED BUS (PORTS 0 AND 2) = NOT AVAILABLE
Figure 10. Memory Map in Nonpartitionable Mode (PM = 1)
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Secure Microprocessor Chip
reached by the expanded bus on ports 0 and 2. An alternate configuration allows dynamic partitioning of a 64kB space as shown in Figure 11. Selecting PES = 1 provides another 64kB of potential data storage or memory-mapped peripheral space as shown in Figure 12. These selections are made using special function registers. The memory map and its controls are covered in detail in the Secure Microcontroller User's Guide. Figure 13 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this configuration, both program and data are stored in a common SRAM chip. Figure 14 shows a similar system with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The bidirectional byte-wide data bus connects the data I/O lines of the SRAM.
DS5003
PROGRAM MEMORY FFFFh
DATA MEMORY (MOVX)
NV RAM DATA
PARTITION
NV RAM PROGRAM
0000h
LEGEND: = NV RAM MEMORY = EXPANDED BUS (PORTS 0 AND 2) = NOT AVAILABLE
Figure 11. Memory Map in Partitionable Mode (PM = 0)
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21
Secure Microprocessor Chip DS5003
PROGRAM MEMORY FFFFh PE4 48kB PARTITION DATA MEMORY (MOVX) 64kB
PE3
32kB
PE2 NV RAM PROGRAM 4000h 16kB
PE1
0000h
LEGEND: = BYTE-WIDE PROGRAM (ENCRYPTED) = NOT ACCESSIBLE
Figure 12. Memory Map with PES = 1
+5V +3V LITHIUM
13 54
VCC VLI
VCCO R/W
12 10 74 2
32 29 22 2
VCC WE CS1 A16 CS2 OE 30 24
DS5003
PORT 0 PORT 1 PORT 2 PORT 3 14 MSEL
CE1 CE2
128kB x 8 SRAM
BA14-BA0 CE3 BD7-BD0 GND 52 16 63 31
A14-A0 A15 D7-D0 GND
Figure 13. Connection to 128kB x 8 SRAM
22 ______________________________________________________________________________________
Secure Microprocessor Chip DS5003
+5V +3V LITHIUM 13 54 VCC VLI R/W VCCO 12 10 74 2 28 27 20 VCC WE CS A14-A0 D7-D0 14 PORT 2 PORT 3 +5V 14 MSEL BD7-BD0 GND 52 28 27 20 VCC WE CS A14-A0 D7-D0 14 GND 32kB x 8 SRAM OE 22 GND 32kB x 8 SRAM OE 22
DS5003
PORT 0 PORT 1
CE1 CE2
BA14-BA0
Figure 14. Connection to 64kB x 8 SRAM
Power Management
The DS5003 monitors VCC to provide power-fail reset, early warning power-fail interrupt, and switchover to lithium backup. It uses an internal bandgap reference in determining the switch points. These are called VPFW, VCCMIN, and VLI, respectively. When VCC drops below V PFW, the DS5003 performs an interrupt and vectors to location 2Bh if the power-fail warning was enabled. Full processor operation continues regardless. When power falls further to VCCMIN, the DS5003 invokes a reset state. No further code execution is performed unless power rises back above V CCMIN. All decoded chip enables and the R/W signal go to an inactive (logic 1) state. VCC is still the power source at this time. When VCC drops further to below VLI, internal circuitry switches to the lithium cell for power. The majority of internal circuits are disabled and the remaining nonvolatile states are retained. Any devices con-
nected to VCCO are powered by the lithium cell at this time. V CCO is at the lithium battery voltage minus approximately 0.45V (less a diode drop), depending on the load. Low-power SRAMs should be used for this reason. When using the DS5003, the user must select the appropriate battery to match the SRAM data-retention current and the desired backup lifetime. Note that the lithium cell is only loaded when VCC < VLI. The Secure Microcontroller User's Guide has more information on this topic. The trip points VCCMIN and VPFW are listed in the electrical specifications.
Package Information
(For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) PACKAGE TYPE 80 MQFP PACKAGE CODE -- DOCUMENT NO. 56-G4005-001
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Secure Microprocessor Chip DS5003
Pin Configuration
P0.5/AD5 P0.6/AD6 P0.7/AD7 CE1N BA11 BA10 N.C. N.C. BD6 BD5 BD7 CE1 PE1 ALE BD4 65 P2.7/A15 66
TOP VIEW
80
79
78
77
76
75
74
73
72
71
70
69
68
P0.4/AD4 CE2 PE2 BA9 P0.3/AD3 BA8 P0.2/AD2 BA13 P0.1/AD1 R/W P0.0/AD0 VCCO VCC MSEL P1.0 BA14 P1.1 BA12 P1.2 BA7 P1.3 PE3 PE4 BA6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
+
67
64 63 62 61 60 59 58 57 56
P2.6/A14 CE3 CE4 BD3 P2.5/A13 BD2 P2.4/A12 BD1 P2.3/A11 BD0 VLI SDI GND P2.2/A10 P2.1/A9 P2.0/A8 XTAL1 XTAL2 P3.7/RD P3.6/WR P3.5/T1 PF VRST P3.4/T0
DS5003
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39 P3.2/INT0
P1.4
BA5
P1.5
BA4
P1.6
BA3
P1.7
PROG
BA2
RST
BA1
P3.0/RXD
BA0
P3.1/TXD
MQFP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
P3.3/INT1
40

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